This application claims the priority benefit of Japanese Patent Application No. 11-306174, filed Oct. 29, 1999, the entire disclosure of which is incorporated herein of reference.
1. Field of the Invention
The invention relates to a signal transmitting circuit having an input node for performing a predetermined process on a signal corresponding to an input signal which is input at an input terminal, specifically from an external device, and for transmitting the processed signal to an internal circuit.
2. Description of the Related Art
Semiconductor integrated circuits (hereinafter xe2x80x9cICsxe2x80x9d), are widely used in electronic devices, such as a personal computer. Such ICs receive a signal from an external above-ranking device or from another device incorporated in the electronic device together with the IC, and performs predetermined processes on the signal.
The ICs described above are prepared to synchronize the input signal to be input with a several kinds of circuits incorporated in the ICs, and to operates a particular circuit incorporated in the ICs based on the input signal. To do so, the IC includes a signal transmitting circuit for performing processes to the input signal, for example, a process for delaying the input signal for a predetermined time or a process for generating a pulse signal having a particular pulse width in response to the input signal.
Typical signal transmitting circuits, which are commonly used in the several circuits, are shown in FIGS. 12 and 13. One signal transmitting circuit 10, shown in FIG. 12, has a delay function and another signal transmitting circuit 15, shown in FIG. 13, has a pulse generating function.
Referring to FIG. 12, the signal transmitting circuit 10 includes a two-input NAND gate 11 and a delay circuit 13. The delay circuit 13 includes an even number of inverters 13-1 . . . 13-k, which are connected in series. The input of the first inverter 13-1 of the delay circuit 13 is connected to an input terminal 1 for receiving an input signal. One of the two inputs of the NAND gate 11 is connected to the input terminal 1, and another input of the NAND gate 11 is connected to the output of the last inverter 13-k of the delay circuit 13. An output terminal 3 is connected to the output of the NAND gate 11. The output terminal 3 is connected to other circuits incorporated in the IC which utilizes the output signal from the output terminal 3.
The operation of the signal transmitting circuit 10 is explained below with reference to FIG. 14. In FIG. 14, a waveform referring to IN shows a voltage level of an input signal at the input terminal 1 shown in FIG. 12. A waveform referring to A shows a voltage level at the output of the last inverter 13-k shown in FIG. 12. A waveform referring to OUT shows a voltage level of the output signal from the NAND gate 11 shown in FIG. 12.
In the initial state of the signal transmitting circuit 10, the input signal IN having a power supply voltage level (hereinafter xe2x80x9cH levelxe2x80x9d), is input at the input terminal 1. Since the voltage at the output of the last inverter 13-k is at the H level, the voltage of the output signal OUT is maintained at a ground level (hereinafter xe2x80x9cL levelxe2x80x9d). For purpose of illustration only, the power supply voltage and the ground voltage are assumed to be five volts (5V) and zero volt (0V), respectively.
At a time t0, when the voltage of the input signal IN, is changed from the H level to the L level, the voltage at the output of the last inverter 13-k is maintained at the L level for a certain time period defined by the number of the inverters 13-1 . . . 13k, because the input signal IN being input to the delay circuit 13 is delayed by the inverters 13-1 . . . 13-k. As a result, the voltage of the output signal OUT is changed to the H level. Then, while the voltage at the output of the last inverter 13-k is changed to the L level, the voltage of the output signal OUT is maintained at the H level.
Assuming that the voltage of the input signal IN is changed to the H level before the time t1, the voltage of the output signal OUT is maintained at the H level because the voltage at the output of the last inverter 13-k is maintained at the L level by delaying the transmittance of the input signal IN. Assuming that the voltage at the output of the last inverter 13-k is changed to the H level, the voltage of the output signal OUT is changed to the L level because the voltages of signals being input to the NAND gate 11 are at the H levels at this moment.
Therefore, the signal transmitting circuit 10 shown in FIG. 12 provides a function for maintaining the voltage of the output signal OUT at the H level during the time period between the time when the voltage level is changed to the H level form the L level and the time t1 corresponding to the delayed time delayed by the delay circuit 13.
Next, the signal transmitting circuit 15 having the pulse generating function is explained with reference to the FIG. 13. In FIG. 13, the same reference numbers as used in FIG. 12 designate the same components. Referring to FIG. 13, the signal transmitting circuit 15 includes a two-input NAND gate 11 and the delay circuit 17. The delay circuit 17 includes an odd number of inverters 17-1 . . . 17-(k+1), which are connected in series. The input of the first invert 17-1 of the delay circuit 17 is connected to an input terminal 1 for receiving an input signal. One of the input of the NAND gate 11 is connected to the input terminal 1, and another input of the NAND gate 11 is connected to the output of the last inverter 17-(k+1) of the delay circuit. An output terminal 3 is connected to the output of the NAND gate 11. The output terminal 3 is connected to other circuits incorporated in the IC, which utilizes the output signal from the output terminal 3. Namely, the only deference is that the delay circuit 17 of the signal transmitting circuit 15 shown in FIG. 13 includes the odd number of inverters while the delay circuit 13 of the signal transmitting circuit 10 shown in FIG. 12 includes the even number of inverters.
The operation of the signal transmitting circuit 15 is explained below with reference to FIG. 15. In FIG. 15, a waveform referring to B shows a voltage level on an output of the last inverter 17-(k+1) shown in FIG. 13. In the initial state of the signal transmitting circuit 15, the input signal IN, having the H level is input at the input terminal 1. Since the voltage at the output of the last inverter 17-(k+1) shows at the L level, the voltage of the output signal OUT is maintained at the H level.
At a time t0, when the voltage level of the input signal IN is changed from the H level to the L level, the voltage at the output of the last inverter 17-(k+1) is maintained at the L level for a certain time period defined by the number of the inverters, because the input signal IN being input to the delay circuit 17 is delayed by the inverters 17-1 . . . 17-(k+1). As a result, the voltage of the output signal OUT is maintained at the H level. Then, while the voltage at the output of the last inverter 17-(k+1) is changed to the H level, the voltage of the output signal OUT is maintained at the H level. Then, while the voltage at the output of the last inverter 17-(k+1) is changed to the L level, the voltage of the output signal OUT is maintained at the H level.
Assuming that the voltage of the input signal IN is changed to the H level before the time t1, the voltage of the output signal OUT is changed to the L level because the voltages of signals being input to the NAND gate 11 are at the H levels at this moment. Assuming that the voltage at the output of the last inverter 17-(k+1) is changed to the L level, the voltage of the output signal OUT is changed to the H level because one of the voltages of signals being input to the NAND gate 11 is at the L levels at this moment.
Therefore, the signal transmitting circuit 15 shown in FIG. 13 provides a function for maintaining the voltage level of the output signal OUT at the L level during the time period that the input signal IN is delayed by the delay circuit 17 so as to generate a pulse signal having a width corresponding to the time period between the time t1 and the time t2. As described above, the signal transmitting circuit processes an input signal and transmits the signal processed to other circuits incorporated in the IC.
If an unexpected signal such as noise is input to the input terminal 1 of these signal transmitting circuits, the operations of these signal transmitting circuits are explained as follows. First, the operation of the signal transmitting circuit 10 shown in FIG. 12 is explained with reference to FIG. 14, assuming that the noise is input to the input terminal 1 at the time t2 and the voltage level of the input signal IN has fallen. If the change of the voltage level of the input signal IN exceeds a threshold voltage of MOS transistors forming the NAND circuit 11 or MOS transistors forming inverters 13-1 through 13-k of the delay circuit 13, the output signal OUT at the output terminal 3 is changed to the H level. Later, since the voltage of the input signal IN is returned to the H level at the time t3, the voltage of the output signal OUT is changed to the L level. However, at the time t4 which is just after the time t3, the voltage at the output of the last inverter 13-k is changed to the L level by the noise that is delayed by the delay circuit 13. Therefore, the voltage of the output signal OUT is changed to the H level again. If the change of the voltage level of the input signal IN caused by the noise appearing at the output terminal 3 as the change of the voltage level of the output signal OUT, the other circuits connected to the output terminal 3 operate unexpectedly as a result of the change of the voltage level of the output signal OUT, which responds to the noise.
Next, the operation of the signal transmitting circuit 15 shown in FIG. 13 is explained with reference to FIG. 15, assuming that the noise is input to the input terminal 1 at the time t3 and the voltage level of the input signal IN has fallen. If the change of the voltage level of the input signal IN exceeds a threshold voltage of MOS transistors forming the NAND circuit 11 or MOS transistors forming inverters 17-1 through 17-(k+1) of the delay circuit 17, the voltage level at the output of the last inverter 17-(k+1) is changed to the H level by the noise that is delayed by the delay circuit 13 at the time t4 after the voltage of the input signal IN is returned to the H level. Therefore, since the voltage of the output signal OUT is changed to the H level, a pulse signal having a short width is generated unexpectedly. If the change of the voltage level of the input signal IN caused by the noise appearing at the output terminal 3 as the change of the voltage level of the output signal OUT, the other circuits connected to the output terminal 3 operate unexpectedly as a result of the change of the voltage level of the output signal OUT, which responds to the noise, as well as the signal transmitting circuit 10 shown in FIG. 12. Accordingly, in the conventional signal transmitting circuit, the IC as a whole is caused to malfunction by noise or an unexpected input signal occurring due to the malfunctioning the external device.
An objective of the invention is to resolve the-above-described problem and to provide a signal transmitting circuit that causes the circuit connected to the output terminal of the signal transmitting circuit not to malfunction as a result of the noise or an unexpected input signal.
A further objective of the invention is provide the above-mentioned signal transmitting circuit suppressing the increase of number of components forming the signal transmitting circuit, the increase of number of output terminal of the IC incorporating the signal transmitting circuit and the increase of number of external control signals which are necessary to achieve the purpose.
The objective is achieved by a signal transmitting circuit for processing an input signal at an input terminal, and for outputting the processed signal from an output terminal, including a control circuit controlling selectively between a first condition and a second condition as to a current pass in response to a control signal, wherein the first condition indicates that the signal is prohibited from transferring to the input node so that a voltage level at the input node is held at a predetermined voltage level, and the second condition indicates that the signal is allowed to transfer to the input node so that a voltage level at the input node is no longer held at the predetermined voltage level.
Further, a signal transmitting circuit includes terminals, which receive external control signals, and a control signal generating circuit.